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YMF754
DS-1E
OVERVIEW
Preliminary
YMF754 (DS-1E) is a high performance audio controller for the PCI Bus. DS-1E consists of two separated functional blocks. One is the PCI Audio block and the other is the Legacy Audio block. PCI Audio block provides 64-voice XG wavetable synthesizer with reverb and variation by using the software driver from YAMAHA. It also supports DirectSound hardware accelerator, Downloadable Sound (DLS) and DirectMusic accelerator. Legacy Audio block supports FM synthesizer, Sound Blaster Pro, MPU401 UART mode and Joystick function in order to provide hardware compatibility for numerous PC games on real DOS without any software driver. DS-1E supports the connection to AC'97 which provides high quality DAC, ADC and analog mixer, and it can connect two AC'97s. In addition, it supports consumer IEC958, Digital Audio Interface (SPDIF In/Out), to connect external audio equipment by digital. In addition to support the same functions of YMF744B (DS-1S), DS-1E adds direct recording function for SPDIF In, and realizes to use SPDIF In and Zoomed Video Port at the same time. And, DS-1E is featured with the capability of dramatically reducing power consumption at normal operation.
FEATURES
* PCI 2.2 Compliant * PC98 / PC99 specification Compliant * PCI Bus Power Management rev. 1.0 Compliant (Support D0, D2 and D3 state) * Supports clock run * PCI Bus Master for PCI Audio True Full Duplex Playback and Capture with different Sampling Rate Maximum 64-voice XG capital Wavetable Synthesizer including GM compatibility DirectSound Hardware Acceleration DirectMusic Hardware Acceleration Downloadable Sound (DLS) level-1 * Legacy Audio compatibility FM Synthesizer Hardware Sound Blaster Pro compatibility MPU401 UART mode MIDI interface Joystick * Supports PC/PCI and Distributed DMA for legacy DMAC (8237) emulation * Supports Serialized IRQ * Supports I2S serial input for Zoomed Video Port * Supports Consumer IEC958 Port (SPDIF In/Out) * Supports direct recording function for SPDIF In * Capability for using SPDIF In and Zoomed Video Port at the same time. * Supports AC'97 Interface (AC-Link) Revision 2.1 * AC'97 Digital Docking * Supports 4-Channel Speaker * Hardware Volume Control * EEPROM Interface * Single Crystal operation (24.576MHz) * Power supply: 3.3V for I/O (5V tolerant), 2.5V for Internal core logic * 128-pin LQFP YMF754-V : 0.5mm pin pitch YMF754-R : 0.4mm pin pitch
The contents of this catalog are target specifications and are subject to change without prior notice. When using this device, please recheck the specifications.
YAMAHA CORPORATION
YMF754 CATALOG December 18, 1998 CATALOG No.:LSI-4MF754A00 June 28, 1999
YMF754
LOGOS
GENERAL MIDI logo is a trademark of Association of Musical Electronics Industry (AMEI), and indicates GM system level 1 Compliant. XG logo is a trademark of YAMAHA Corporation. SONDIUS-XG logo is a trademark that Stanford University in the United States and YAMAHA Corporation hold jointly. Sensaura logo is a trademark of Central Research Laboratories Limited.
1. GM system level 1 GM system level 1 is a world standard format about MIDI synthesizer which provides voice arrangements and MIDI functions. 2. XG XG is a format about MIDI synthesizer that is proposed by YAMAHA, and keeps the upper compatibility of GM system level 1. 3. SONDIUS-XG Products bearing the SONDIUS-XG logo are licensed under patents of Stanford University and YAMAHA Corporation as listed on . The SONDIUS-XG produces acoustic sound Therefore, it provides outputs by running a virtual simulation of the actual acoustic instrument operation. that simply processes the recorded acoustic sound sources only. of virtual acoustic sound to the XG format. 4. Sensaura Sensaura is a technology which provides 3D positional audio and moving effect by HRTF (Head Related Transfer Function) with 2 speakers or headphone. This feature makes it possible to enjoy invariable and unchangeable sound feelings in all-positional area covering as wide as 360 degrees. The good points are the voice arrangements kept extensively, a large number of the voices, modification of the voices, 3 kinds of effects, and so on.
much more real-world acoustic sound outputs fundamentally different from the Wavetable sound generator The SONDIUS-XG adds the technology
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YMF754
PIN CONFIGURATION
YMF754-V (0.5mm pin pitch)
AD26 PVDD2 AD25 AD24 CBE3# IDSEL AD23 PVSS4 AD22 AD21 AD20 AD19 AD18 AD17 AD16 CBE2# PVSS3 FRAME# IRDY# TRDY# DEVSEL# PVDD1 STOP# PERR# SERR# PAR CBE1# PVSS2 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 PVSS1 CBE0#
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103
AD27 AD28 PVSS5 AD29 AD30 AD31 REQ# GNT# PCICLK RST# PVSS6 PVDD3 RESERV0 INTA# CVDD2 RESERV1 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 TXD RXD
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
TEST# VDD2 VSS2 VDD1 CMCLK CSDO CBCLK CSDI0 CSYNC CRST# VDD0 VSS1 RESERV2 RESERV3 CSDI1 DOCKEN# LVSS XI24 XO24 LOOPF LVDD CVDD1 ZVBCLK ZVLRCK ZVSDI SPDIFOUT SPDIFIN IRQ11 IRQ10 IRQ9 IRQ7 IRQ5 GPIO2 GPIO1 GPIO0 RESERV4 RESERV5 RESERV6
AD7 AD6 AD5 PVDD0 AD4 AD3 AD2 AD1 PVSS0 AD0 SERIRQ# PCGNT# PCREQ# CLKRUN# CVDD0 ROMDI ROMDO/VOLDW# ROMSK/VOLUP# ROMCS RESERV12 RESERV11 RESERV10 RESERV9 RESERV8 RESERV7 VSS0
128 Pin LQFP Top View
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YMF754
YMF754-R (0.4mm pin pitch)
AD24 CBE3# IDSEL AD23 PVSS4 AD22 AD21 AD20 AD19 AD18 AD17 AD16 CBE2# PVSS3 FRAME# IRDY# TRDY# DEVSEL# PVDD1 STOP# PERR# SERR# PAR CBE1# PVSS2 AD15 AD14 AD13 AD12 AD11 AD10 AD9
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97
AD25 PVDD2 AD26 AD27 AD28 PVSS5 AD29 AD30 AD31 REQ# GNT# PCICLK RST# PVSS6 PVDD3 RESERV0 INTA# CVDD2 RESERV1 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 TXD RXD TEST# VDD2 VSS2 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
VDD1 CMCLK CSDO CBCLK CSDI0 CSYNC CRST# VDD0 VSS1 RESERV2 RESERV3 CSDI1 DOCKEN# LVSS XI24 XO24 LOOPF LVDD CVDD1 ZVBCLK ZVLRCK ZVSDI SPDIFOUT SPDIFIN IRQ11 IRQ10 IRQ9 IRQ7 IRQ5 GPIO2 GPIO1 GPIO0
AD8 PVSS1 CBE0# AD7 AD6 AD5 PVDD0 AD4 AD3 AD2 AD1 PVSS0 AD0 SERIRQ# PCGNT# PCREQ# CLKRUN# CVDD0 ROMDI ROMDO/VOLDW# ROMSK/VOLUP# ROMCS RESERV12 RESERV11 RESERV10 RESERV9 RESERV8 RESERV7 VSS0 RESERV6 RESERV5 RESERV4
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
128 Pin LQFP Top View
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YMF754
PIN DESCRIPTION 1. PCI Bus Interface (54-pin)
Name PCICLK RST# AD[31:0] C/BE[3:0]# PAR FRAME# IRDY# TRDY# STOP# IDSEL DEVSEL# REQ# GNT# PCREQ# PCGNT# PERR# SERR# INTA# SERIRQ# CLKRUN# I/O I I IO IO IO IO IO IO IO I IO O I O I IO O O IO IO Type P P Ptr Ptr Ptr Pstr Pstr Pstr Pstr P Pstr P P Ptr Ptr Pstr Pod Pod Ptr Ptr Size PCI Clock Reset Address / Data Command / Byte Enable Parity Frame Initiator Ready Target Ready Stop ID Select Device Select PCI Bus Master Request PCI Bus Master Grant PC/PCI Request PC/PCI Grant Parity Error System Error Interrupt signal output for PCI Bus Serialized IRQ Clock Run Function
2. AC'97 Interface (8-pin)
Name CRST# CMCLK CBCLK CSDO CSYNC CSDI0 CSDI1 DOCKEN# I/O O O I O O I I I Type T C T T T T Tup Tup Size 6mA 6mA 6mA Function Reset signal for AC'97 Master Clock for AC'97 (24.576MHz) AC-link: Bit Clock for AC'97 audio data AC-link: AC'97 Serial audio output data AC-link: AC'97 Synchronized signal AC-link: AC'97 Serial audio input data (Primary) AC-link: AC'97 Serial audio input data (Secondary) Secondary AC'97 Enable
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YMF754
3. External Audio Interface (5-pin)
Name SPDIFOUT SPDIFIN ZVBCLK ZVLRCK ZVSDI I/O O I I I I Type T Tup Tup Tup Tup Size 2mA Function Digital Audio Interface output Digital Audio Interface input Zoomed Video Port Zoomed Video Port Zoomed Video Port Bit Clock L/R Clock Serial Data
4. Legacy Device Interface (15-pin)
Name I/O Type Size Function Interrupt 5 of Legacy Audio IRQ5 IRQ7 IRQ9 IRQ10 IRQ11 GP[3:0] GP[7:4] RXD TXD O O O O O I I I O Ttr Ttr Ttr Ttr Ttr A Tup Tup T 6mA 6mA 6mA 6mA 6mA 2mA It is directly connected to the interrupt signal of System I/O chip. Interrupt 7 of Legacy Audio Interrupt 9 of Legacy Audio Interrupt 10 of Legacy Audio Interrupt 11 of Legacy Audio. Joystick Port Joystick Port MIDI Data Receive MIDI Data Transfer
5. Miscellaneous (11-pin)
Name ROMCS ROMSK / VOLUP# ROMDO / VOLDW# ROMDI XI24 XO24 LOOPF GPIO[2:0] TEST# I/O O IO IO I I O I IO I Type T Tup Tup Tup C C A Tup Tup Size 2mA 2mA 2mA 6mA Function Chip select for external EEPROM Serial clock for external EEPROM or Hardware Volume (Up) Serial data output for external EEPROM or Hardware Volume (Down) Serial data input for external EEPROM 24.576 MHz Crystal 24.576 MHz Crystal Capacitor for PLL General purpose Input / Output GPIO2 can use for a reset pin of Secondary AC'97. LSI Test pin (Do not connect externally.)
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YMF754
6. Power Supply (22-pin)
Name PVDD[3:0] PVSS[6:0] CVDD[2:0] VDD[2:0] VSS[2:0] LVDD LVSS I/O Type Size Function 3.3V Power supply for PCI Bus Interface Ground for PCI Bus Interface 2.5V Power supply for Core logic 3.3V Power supply Ground 2.5V Power supply for PLL Filter Ground for PLL Filter
7. Reserve Pin (13-pin)
Name RESERV[12:0] I/O Type Size Function Reserve pins (Do not connect externally.)
TYPE
T : TTL Ttr : Tri-State TTL Tup : Pull up (Max. 300kohm) TTL A : Analog C : CMOS P : PCI Ptr : Tri-State PCI Pstr : Sustained Tri-Sate PCI Pod : Open Drain PCI
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YMF754
BLOCK DIAGRAM
EEPROM I/F GPIO Clock Run PCI Side Band PC/PCI S-IRQ ZV Port SPDIF Input Legacy Audio FM Synthesizer SB Pro D-DMA Engine PCI Interface MPU401 Joystick Sampling Rate Converter (SRC) AC-link Interface SPDIF Output
PCI Bus Master DMA Controller Audio Function Config Register
PCI Audio XG Synthesizer DirectSound Acc. Wave In/Out
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YMF754
FUNCTION OVERVIEW 1. PCI INTERFACE
DS-1E supports the PCI bus interface and complies to PCI revision 2.2.
1-1. PCI Bus Command
DS-1E supports the following PCI Bus commands. 1-1-1. Target Device Mode C/BE[3:0]# 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Command Interrupt Acknowledge (not support) Special Cycle (not support) I/O Read I/O Write reserved reserved Memory Read Memory Write reserved reserved Configuration Read Configuration Write Memory Read Multiple (alias to memory read) Dual Address Cycle (not support) Memory Read Line (alias to memory read) Memory Write and Invalidate (alias to memory write)
DS-1E does not assert DEVSEL# when accessed with commands that are indicated as (not supported) or reserved.
1-1-2. Master Device Mode C/BE[3:0]# 0 0 1 1 1 1 0 1 Command Memory Read Memory Write
When DS-1E becomes a Master Device, it generates only memory write and read cycle commands.
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YMF754
1-2. PCI Configuration Register
In addition to the Configuration Register defined by PCI Revision 2.2, DS-1E provides proprietary PCI Configuration Registers in order to control legacy audio function, such as FM Synthesizer, Sound Blaster Pro, MPU401 and Joystick. These additional registers are configured by BIOS or the configuration software from YAMAHA Corporation. The following shows the overview of the PCI Configuration Register.
Offset 00-03h 04-07h 08-0Bh 0C-0Fh 10-13h 14-17h 18-1Bh 1C-2Bh 2C-2Fh 30-33h 34-37h 38-3Bh 3C-3Fh 40-43h 44-47h 48-4Bh 4C-4Fh 50-53h 54-57h 58-5Bh 5C-5Fh 60-63h 64-67h 68-FFh
b[31..24] Device ID Status Base Class Code Reserved
b[23..16]
b[15..8] Vendor ID Command Programming IF Latency Timer
b[7..0]
Sub Class Code Header Type
Revision ID Reserved
PCI Audio Memory Base Address Legacy Audio I/O Base Address (Dummy for SB, FM, MPU, D-DMA) Legacy Audio I/O Base Address (Dummy for Joystick) Reserved Subsystem ID Reserved Reserved Reserved Maximum Latency Minimum Grant Interrupt Pin Interrupt Line Cap Pointer Subsystem Vendor ID
Extended Legacy Audio Control Subsystem ID Write DS-1E Power Control 1 DS-1E Power Control 2 Power Management Capabilities Reserved DS-1E Secondary AC'97 Power Control Reserved Sound Blaster Base Address Joystick Base Address Reserved
Legacy Audio Control Subsystem Vendor ID Write DS-1E Control D-DMA Slave Configuration Next Item Pointer Capability ID
Power Management Control / Status ACPI Mode
FM Synthesizer Base Address MPU401 Base Address
Reserved
registers are hardwired to "0".
All data written to these registers are discarded.
The values
read from these registers are all zero. DS-1E can be accessed by using any bus width, 8-bit, 16-bit or 32-bit.
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YMF754
00-01h: Vendor ID
Read Only Default: 1073h Access Bus Width: 8, 16, 32-bit
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Vendor ID
b[15:0] ........Vendor ID This register contains the YAMAHA Vendor ID registered in Revision 2.2. 1073h. This register is hardwired to
02-03h: Device ID
Read Only Default: 0012h Access Bus Width: 8, 16, 32-bit
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Device ID
b[15:0] ........Device ID This register contains the Device ID of DS-1E. This register is hardwired to 0012h.
04-05h: Command
Read / Write Default: 0000h Access Bus Width: 8, 16, 32-bit
b15 b14 b13 b12 b11 b10 b9 b8 SER b7 b6 PER b5 b4 b3 b2 BME b1 MS b0 IOS
b0................IOS: I/O Space This bit is a dummy one that is capable of writing. includes I/O devices. b1................MS: Memory Space This bit enables DS-1E to response to Memory Space Access. "0": DS-1E ignores Memory Space Access. "1": DS-1E responds to Memory Space Access. b2................BME: Bus Master Enable This bit enables DS-1E to act as a master device on the PCI bus. "0": Do not set DS-1E to be the master device. "1": Set DS-1E to be the master device. (default) (default) This bit indicates for BIOS or OS that DS-1E
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YMF754
b6................PER: Parity Error Response This bit enables DS-1E responses to Parity Error. "0": DS-1E ignores all parity errors. (default) "1": DS-1E performs error operation when DS-1E detects a parity error. b8................SER: SERR# Enable This bit enables DS-1E to drive SERR#. "0": Do not drive SERR#. Error on special cycle. (default) "1": Drives SERR# when DS-1E detects an Address Parity Error on normal target cycle or a Data Parity
06-07h: Status
Read / Write Clear Default: 0210h Access Bus Width: 8, 16, 32-bit
b15 DPE b14 SSE b13 RMA b12 RTA b11 STA b10 b9 b8 DPD b7 b6 b5 b4 CAP b3 b2 b1 b0 DEVT
b4................CAP: Capability
(Read Only) This bit is read only. When 58-59h :
This bit indicates that DS-1E supports the capability register.
ACPI Mode register, ACPI bit is "0", the bit is "1". When ACPI bit is "1", the bit is "0". b8................DPD: Data Parity Error Detected This bit indicates that DS-1E detects a Data Parity Error during a PCI master cycle. b[10:9] ........DEVT: DEVSEL Timing (Read Only)
This bit indicates that the decoding speed of DS-1E is Medium. b11..............STA: Signaled Target Abort This bit indicates that DS-1E terminates a transaction with Target Abort during a target cycle. b12..............RTA: Received Target Abort This bit indicates that a transaction is terminated with Target Abort while DS-1E is in the master memory cycle. b13..............RMA: Received Master Abort This bit indicates that a transaction is terminated with Master Abort while DS-1E is in the master memory cycle. b14..............SSE: Signaled System Error This bit indicates that DS-1E asserts SERR#. b15..............DPE: Detected Parity Error This bit indicates that DS-1E detects Address Parity Error or Data Parity Error during a transaction.
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YMF754
08h: Revision ID
Read Only Default: 00h Access Bus Width: 8, 16, 32-bit
b7 b6 b5 b4 b3 b2 b1 b0 Revision ID
b[7:0] ..........Revision ID This register contains the revision number of DS-1E. This register is hardwired to 00h.
09h: Programming Interface
Read Only Default: 00h Access Bus Width: 8, 16, 32-bit
b7 b6 b5 b4 b3 b2 b1 b0 Programming Interface
b[7:0] ..........Programming Interface This register indicates the programming interface of DS-1E. This register is hardwired to 00h.
0Ah: Sub-class Code
Read Only Default: 01h Access Bus Width: 8, 16, 32-bit
b7 b6 b5 b4 b3 b2 b1 b0 Sub-class Code
b[7:0] ..........Sub-class Code This register indicates the sub-class of DS-1E. Audio Sub-class. This register is hardwired to 01h. DS-1E belongs to the
0Bh: Base Class Code
Read Only Default: 04h Access Bus Width: 8, 16, 32-bit
b7 b6 b5 b4 b3 b2 b1 b0 Base Class Code
b[7:0] ..........Base Class Code This register indicates the base class of DS-1E. the Multimedia Base Class. This register is hardwired to 04h. DS-1E belongs to
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YMF754
0Dh: Latency Timer
Read / Write Default: 00h Access Bus Width: 8, 16, 32-bit
b7 b6 b5 b4 b3 b2 b1 b0 Latency Timer
b[7:0] ..........Latency Timer When DS-1E becomes a Bus Master device, this register indicates the initial value of the Master Latency Timer.
0Eh: Header Type
Read Only Default: 00h Access Bus Width: 8, 16, 32-bit
b7 b6 b5 b4 b3 b2 b1 b0 Header Type
b[7:0] ..........Header Type This register indicates the device type of DS-1E. This is hardwired to 00h.
10-13h: PCI Audio Memory Base Address
Read / Write Default: 00000000h Access Bus Width: 8, 16, 32-bit
b15 MBA b31 b14 b30 b13 b29 b12 b28 b11 b27 b10 b26 b9 b25 b8 b24 b7 b23 b6 b22 b5 b21 b4 b20 b3 b19 b2 b18 b1 b17 b0 b16
MBA (higher)
b[31:15] ......MBA: Memory Base Address This register indicates the physical Memory Base address of the PCI Audio registers in DS-1E. address can be located anywhere in the 32-bit address space. prefetchable. Size of the register to be mapped into the memory space is 32,768 bytes. The base
Data in the DS-1E register is not
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YMF754
14-17h: Legacy Audio I/O Base Address (Dummy for SB, FM, MPU, D-DMA)
Read / Write Default: 00000001h Access Bus Width: 8, 16, 32-bit
b15 b31 b14 b30 b13 b29 b12 b28 b11 b27 b10 b26 b9 b25 b8 b24 b7 b23 b6 b22 b5 b21 b4 b20 b3 b19 b2 b18 b1 b17 b0 I/O b16 IOBASE0
b0................IO
(Read Only)
This bit indicates that the base address is assigned to I/O. This bit is hardwired to "1". b[15:6] ........IOBASE0 This register is used so that the OS may secure I/O resources for Sound Blaster Pro, FM Synthesizer, MPU401 and D-DMA controller. driver. Because this register is a dummy one, each for the I/O addresses of the above blocks is assigned with the I/O addresses set to 4C-4Dh and 60-65h respectively by the software
18-1Bh: Legacy Audio I/O Base Address (Dummy for Joystick)
Read / Write Default: 00000001h Access Bus Width: 8, 16, 32-bit
b15 b31 b14 b30 b13 b29 b12 b28 b11 b27 b10 b26 b9 b25 b8 b24 b7 b23 b6 b22 b5 b21 b4 b20 b3 b19 b2 b18 b1 b17 b0 I/O b16 IOBASE1
b0................IO
(Read Only)
This bit indicates that the base address is assigned to I/O. This bit is hardwired to "1". b[15:2] ........IOBASE1 This register is used so that the OS may secure I/O resource for the joystick port. driver. Because this register is
a dummy one, the joystick I/O address is assigned with the I/O address set to 66-67h by the software
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YMF754
2C-2Dh: Subsystem Vendor ID
Read Only Default: 1073h Access Bus Width: 8, 16, 32-bit
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Subsystem Vendor ID
b[15:0] ........Subsystem Vendor ID This register contains the Subsystem Vendor ID. In general, this ID is used to distinguish adapters or This register is read only. To IHVs must change this
systems made by different IHVs using the same chip by the same vendor. ID to their Vendor ID in the BIOS POST routine.
write the IHV's Vendor ID, use 44-45h (Subsystem Vendor ID Write Register).
In case of the system such as Sound Card which BIOS can not control, this ID can be changed by connecting EEPROM externally. Then, Subsystem Vendor ID Write Register is invalid. In case EEPROM is not externally, the default value is the YAMAHA's Vendor ID, 1073h.
2E-2Fh: Subsystem ID
Read Only Default: 0012h Access Bus Width: 8, 16, 32-bit
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Subsystem ID
b[15:0] ........Subsystem ID This register contains the Subsystem ID. In general, this ID is used to distinguish adapters or systems This register is read only. To write IHVs must change this ID to their ID
made by different IHVs using the same chip by the same vendor. the IHV's Device ID, use 46-47h (Subsystem ID Write Register). in the BIOS POST routine.
In case of the system such as Sound Card which BIOS can not control, this ID can be changed by connecting EEPROM externally. Then, Subsystem ID Write Register is invalid. In case EEPROM is not externally, the default value is the YAMAHA's Device ID, 0012h.
34h: Capability Register Pointer
Read Only Default: 50h Access Bus Width: 8, 16, 32-bit
b7 b6 b5 b4 b3 b2 b1 b0 Capability Register Pointer
b[7:0] ..........Capability Register Pointer This register indicates the offset address of the Capabilities register in the PCI Configuration register when 58-59h: ACPI Mode register, ACPI bit is "0". registers as the capabilities. Configuration register, and this register indicates "50h". When ACPI bit is "1", this register indicates "00h". DS-1E provides PCI Bus Power Management The Power Management registers are mapped to 50h - 55h in the PCI
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YMF754
3Ch: Interrupt Line
Read / Write Default: 00h Access Bus Width: 8, 16, 32-bit
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt Line
b[7:0] ..........Interrupt Line This register indicates the interrupt channel that INTA# is assigned to.
3Dh: Interrupt Pin
Read Only Default: 01h Access Bus Width: 8, 16, 32-bit
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt Pin
b[7:0] ..........Interrupt Pin DS-1E supports INTA# only. This register is hardwired to 01h.
3Eh: Minimum Grant
Read Only Default: 05h Access Bus Width: 8, 16, 32-bit
b7 b6 b5 b4 b3 b2 b1 b0 Minimum Grant
b[7:0] ..........Minimum Grant This register indicates the length of the burst period required by DS-1E. This register is hardwired to 05h.
3Fh: Maximum Latency
Read Only Default: 19h Access Bus Width: 8, 16, 32-bit
b7 b6 b5 b4 b3 b2 b1 b0 Maximum Latency
b[7:0] ..........Maximum Latency This register indicates how often DS-1E generates the Bus Master Request. This register is hardwired to 19h.
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YMF754
40-41h: Legacy Audio Control
Read / Write Default: 907Fh Access Bus Width: 8, 16, 32-bit
b15 LAD b14 SIEN b13 b12 MPUIRQ b11 b10 b9 SBIRQ b8 b7 b6 b5 I/O b4 MIEN b3 MEN b2 b1 b0 SDMA JPEN FMEN SBEN
b0................SBEN: Sound Blaster Enable This bit enables the mapping of the Sound Blaster Pro block in the I/O space specified by 62-63h: Sound Blaster Base Address register, when LAD is set to "0". "0": Disable the mapping of the SB block to the I/O space "1": Enable the mapping of the SB block to the I/O space b1................FMEN: FM Synthesizer Enable This bit enables the mapping of the FM Synthesizer block in the I/O space specified by 60-61h: FM Synthesizer Base Address register when LAD is set to "0". FM Synthesizer registers can be accessed via SB I/O space, while the SB block is enabled, even if FMEN is set to "0". "0": Disable the mapping of the FM Synthesizer block to the FMIO space "1": Enable the mapping of the FM Synthesizer block to the FMIO space (default) After setting FMEN to "1", about 100 msec is necessary before accessing these I/O space. b2................JPEN: Joystick Port Enable This bit enables the mapping of the Joystick block in the I/O space specified by 66-67h: Joystick Base Address register, when LAD is set to "0". "0": Disable the mapping of the Joystick block "1": Enable the mapping of the Joystick block b3................MEN: MPU401 Enable This bit enables the mapping of the MPU401 block in the I/O space specified by 64-65h: MPU401 Base Address register, when LAD is set to "0". "0": Disable the mapping of the MPU401 block "1": Enable the mapping of the MPU401 block b4................MIEN: MPU401 IRQ Enable This bit enables the interrupt service of MPU401, when LAD is set to "0" and MEN is set to "1". MPU401 generates an interrupt signal when it receives any kind of MIDI data from the RXD pin. "0": The MPU401 block can not use the interrupt service. "1": The MPU401 block can use interrupt signals determined by the MPUIRQ bits. b5................I/O: I/O Address Aliasing Control This bit selects the number of bits to decode for the I/O address of each block. "0": 16-bit address decode "1": 10-bit address decode (default) (default) (default) (default) (default)
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YMF754
b[7:6] ..........SDMA: Sound Blaster DMA-8 Channel Select These bits select the DMA channel for the Sound Blaster Pro block. "0": "1": "2": "3": DMA ch0 DMA ch1 reserved DMA ch3 (default)
b[10:8] ........SBIRQ: Sound Blaster IRQ Channel Select These bits select the interrupt channel for the Sound Blaster Pro block. "0": "1": "2": "3": "4": "5" - "7": IRQ5 IRQ7 IRQ9 IRQ10 IRQ11 reserved. (default)
b[13:11] ......MPUIRQ: MPU401 IRQ Channel Select When MIEN is set to "1", these bits select the interrupt channel for the MPU401 block. "0": "1": "2": "3": "4": "5" - "7": IRQ5 IRQ7 IRQ9 IRQ10 IRQ11 reserved (default)
Same interrupt channels can be assigned to SBIRQ and MPUIRQ. b14..............SIEN: Serialized IRQ enable DS-1E supports 3 types of interrupt protocols: PCI interrupt (INTA#), Legacy interrupt (IRQs) and Serialized IRQ. The interrupt protocol is selected with IMOD and SIEN as follows. Only one The interrupt channels for IRQs and Serialized IRQ are determined by SBIRQ and MPUIRQ,. protocol can be used at once. SIEN 0 0 1 1 IMOD 0 1 0 1 Interrupt protocol Legacy interrupt (IRQs) PCI interrupt (INTA#) Serialized IRQ reserved (default)
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YMF754
b15..............LAD: Legacy Audio Disable This bit disables the Legacy Audio block. "0": Enables the Legacy Audio block "1": Disables the Legacy Audio block the PCI bus. (default) When this bit is set to "1", DS-1E does not respond to the I/O Target transaction for legacy I/O address on
42-43h: Extended Legacy Audio Control
Read / Write Default: 0000h Access Bus Width: 8, 16, 32-bit
b15 IMOD b14 b13 b12 b11 b10 b9 b8 MAIM b7 b6 b5 b4 b3 b2 b1 b0 SBVER SMOD
b8................MAIM: MPU401 Acknowledge Interrupt Mask This bit determine whether interrupt is asserted when the acknowledge, which is occurred by changing MPU401 mode form default to UART, is returned. "0": Interrupt is asserted when the acknowledge is returned. "1": Interrupt is masked when the acknowledge is returned. b[12:11] ......SMOD: SB DMA mode These bits determine the protocol to achieve the DMAC(8237) function on the PCI bus. "0": "1": "2": "3" PC/PCI reserved Distributed DMA (D-DMA) reserved (default) (default)
b[14:13] ......SBVER: SB Version Select These bits set the version of the SB Pro DSP. DSP command. "0": "1": "2": "3": ver 3.01 ver 2.01 ver 1.05 reserved (default) The value set in these bits is returned by sending the E1h
b15..............IMOD: Legacy IRQ mode The legacy interrupt protocol is selected with IMOD and SIEN. Refer to the explanation of SIEN bit.
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YMF754
44-45h: Subsystem Vendor ID Write
Read / Write Default: 1073h Access Bus Width: 16-bit
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Subsystem Vendor ID Write
b[15:0] ........Subsystem Vendor ID Write This register sets the Subsystem Vendor ID that is read from 2C-2Dh (Subsystem Vendor ID register). The default value is the YAMAHA Vendor ID, 1073h. the BIOS POST routine. In case EEPROM connects externally, this register is invalid, and do not reflect to Subsystem Vendor ID. IHVs must change this ID to their Vendor ID in
46-47h: Subsystem ID Write
Read / Write Default: 0012h Access Bus Width: 16-bit
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Subsystem ID Write
b[15:0] ........Subsystem ID Write This register sets the Subsystem ID that is read from 2E-2Fh (Subsystem ID register). The default value is the DS-1E Device ID, 0012h. POST routine. In case EEPROM connects externally, this register is invalid, and do not reflect to Subsystem ID. IHVs must change this ID to their ID in the BIOS
48-49h: DS-1E Control
Read / Write Default: 0001h Access Bus Width: 8, 16, 32-bit
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 CRST ACLS WRST
b0................CRST: AC'97 Software Reset Signal Control This bit controls the CRST# signal. "0": Inactive (CRST#=High) "1": Active (CRST#=Low) (default)
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YMF754
b2................WRST: AC'97 Warm Reset This bit places the AC'97 in warm reset condition when the BIT_CLK signal on the AC'97 remains in inactive state. If this bit is set to "1", it will automatically return to "0" after 1.3s time duration. This bit is valid only while the ACLS bit is set to "0". "0": Normal (default) Except in this case, even if this bit is attempted to be
set to "1", no warm reset will be generated (write operation of "1" remains disabled). "1": AC'97 Warm Reset b3................ACLS: AC-Link Status (Read Only) This bit is "1" when the AC-link remains in
This bit indicates whether or not the AC-link is active. active state (the BIT_CLK signal is active). "0": AC'97 Inactive "1": AC'97 Active (default)
4A-4Bh: DS-1E Power Control 1
Read / Write Default: 0000h Access Bus Width: 8, 16, 32-bit
b15 PR7 b14 PR6 b13 PR5 b12 PR4 b11 PR3 b10 PR2 b9 PR1 b8 PR0 b7 b6 JSR b5 b4 b3 b2 DPLL b1 b0 DMC
b0................DMC: Disable Master Clock Oscillation Setting this bit to "1" disables the oscillation of the Master Clock (24.576 MHz). "0": Normal "1": Disable b2................DPLL: Disable PLL Clock Oscillation Setting this bit to "1" disables the oscillation of PLL. "0": Normal "1": Disable b6................JSR: Joystick Reset This bit controls reset of the flip-flop circuit following the analog comparator stage on the joystick port. The Initial value is set to "0" immediately after power on reset or hardware reset. "0": Normal (default) "1": Resets the flip-flop circuit following the analog comparator stage on the joystick port b8................PR0: AC'97 Power Down Control 0 This bit controls the power state of the ADC and Input Mux in the Primary AC'97. "0": Normal "1": Power down (default) (default) (default)
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YMF754
b9................PR1: AC'97 Power Down Control 1 This bit controls the power state of the DAC in the Primary AC'97. "0": Normal "1": Power down b10..............PR2: AC'97 Power Down Control 2 This bit controls the power state of the Analog Mixer (Vref still on) in the Primary AC'97. state retains the Reference Voltage of the AC'97. "0": Normal "1": Power down b11..............PR3: AC'97 Power Down Control 3 This bit controls the power state of the Analog Mixer (Vref off) in the Primary AC'97. state removes Reference Voltage of the AC'97. "0": Normal "1": Power down b12..............PR4: AC'97 Power Down Control 4 This bit controls the power state of the AC-link in the Primary AC'97. "0": Normal "1": Power down b13..............PR5: AC'97 Power Down Control 5 Setting this bit to "1" disables the internal clock of the Primary AC'97. DS-1E, the master clock is supplied from DS-1E. "0": Normal "1": Disable b14..............PR6: AC'97 Power Down Control 6 This bit controls PR6 bit status of the power control register in the Primary AC'97. b15..............PR7: AC'97 Power Down Control 7 This bit controls PR7 bit status of the power control register in the Primary AC'97. Respective data set to b[15:8] are correspondingly set into the "Power down Ctrl/Stat" register in the Primary AC'97 via the AC-Link. These are not set into the "Power down Ctrl/Stat" register in the Secondary AC'97. (default) In case the AC'97 is used with (default) (default) This power (default) This power (default)
Therefore, when the clock is stopped completely, set
PR5 bits to "1" firstly, then the CMCD bit should be set to "1" after duration of 1ms or longer.
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YMF754
4C-4Dh: D-DMA Slave Configuration
Read / Write Default: 0000h Access Bus Width: 8, 16, 32-bit
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 EA b2 TS b1 b0 CE Base Address
b0................CE: Channel Enable This bit enables the Distributed DMA function. "0": Disable Distributed DMA "1": Enable Distributed DMA b[2:1] ..........TS: Transfer Size (Read Only) (default)
These bits indicate the size of the DMA transfer. Since DS-1E supports only 8-bit DMA transfer, the bits are hardwired to 00b. b3................EA: Extended Address (Read Only) This bit is hardwired to 0b.
DS-1E does not support extended address mode.
b[15:4] ........Base Address : D-DMA Slave Base Address These bits indicate the D-DMA slave base address.
4E-4Fh: DS-1E Power Control 2
Read / Write Default: 0000h Access Bus Width: 8, 16, 32-bit
b15 b14 b13 b12
PSHWV
b11
PSIO
b10
b9
b8
PSDIT
b7
PSZV
b6
b5
b4
b3
b2
b1
PSFM
b0
CMCD
PSACL PSDIR
PSSRC PSPCA PSJOY PSMPU PSSB
b0................CMCD: CODEC Master Clock Disable Setting this bit to "1" disables the oscillation of the CMCLK. To stop a clock, when the CMCLK is (If the Secondary
supplied to the AC'97, it is required that b13:PR5 bit of 4A-4Bh register is set to "1". AC'97 is used, it is also necessary that b5:SPR5 bit of 5A-5Bh register is set to "1".) "0": Normal "1": Disable b1................PSFM: Power Save FM Synthesizer Setting this bit to "1" stops a clock supplied to the FM synthesizer block. "0": Normal "1": Disable b2................PSSB: Power Save Sound Blaster Setting this bit to "1" stops a clock supplied to the Sound Blaster block. "0": Normal "1": Disable (default) (default) (default)
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YMF754
b3................PSMPU: Power Save MPU401 Setting this bit to "1" stops a clock supplied to the MPU401 block. "0": Normal "1": Disable b4................PSJOY: Power Save Joystick Setting this bit to "1" disables the comparator of the Joystick block. "0": Normal "1": Disable b5................PSPCA: Power Save PCI Audio Setting this bit to "1" stops a clock supplied to the PCI Audio block. "0": Normal "1": Disable b6................PSSRC: Power Save SRC Setting this bit to "1" stops a clock supplied to the SRC block. "0": Normal "1": Disable b7................PSZV: Power Save Zoomed Video port Setting this bit to "1" stops a clock supplied to the Zoomed Video port block. "0": Normal "1": Disable b8................PSDIT: Power Save Digital Audio Interface Transmitter Setting this bit to "1" stops a clock supplied to the DIT (SPDIF OUT) block. "0": Normal "1": Disable b9................PSDIR: Power Save Digital Audio Interface Receiver Setting this bit to "1" stops a clock supplied to the DIR (SPDIF IN) block. "0": Normal "1": Disable b10..............PSACL: Power Save AC-Link Setting this bit to "1" stops a clock supplied to the AC-Link block. "0": Normal "1": Disable (default) (default) (default) (default) (default) (default) (default) (default)
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YMF754
b11..............PSIO: Power Save I/O Pad Setting this bit to "1" cuts the pull up resistor of the input pins except for the PCI interface and AC-Link. The input signals keep the level before PSIO bit is set from "0" to "1". "low", the pull up resistor is cut. "0": Normal (default) "1": Cuts the pull up resistor b12..............PSHWV: Power Save Hardware Volume Setting this bit to "1" stops a clock supplied to the Hardware Volume block. "0": Normal "1": Disable (default) In case the input level is only
CMCD PSFM PSSB PSMPU PSJOY Master Clock (24.576MHz) PSPCA PLL PSSRC PSZV DMC DPLL PSDIT PSDIR PSHWV PSACL
AC97 Master Clock FM Synthesizer SB Pro MPU401 Joystick PCI Audio SRC ZVport SPDIF OUT SPDIF IN H/W Vol. AC-link
PCI Clock (33MHz)
PCI I/F PC/PCI D-DMA S-IRQ EEPROM I/F
External Input
PSIO
I/O Pad
Power Management Block
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YMF754
50h: Capability ID
Read Only Default: 01h Access Bus Width: 8, 16, 32-bit
b7 b6 b5 b4 b3 b2 b1 b0 Capability ID
b[7:0] ..........Capability ID: Capability Identifier This register indicates that the new capability register is for Power Management control. hardwired to 01h. This register is
51h: Next Item Pointer
Read Only Default: 00h Access Bus Width: 8, 16, 32-bit
b7 b6 b5 b4 b3 b2 b1 b0 Next Item Pointer
b[7:0] ..........Next Item Pointer DS-1E does not provide other new capability besides Power Management. 00h. This register is hardwired to
52-53h: Power Management Capabilities
Read Only Default: 0401h Access Bus Width: 8, 16, 32-bit
b15 b14 b13 b12 b11 b10 D2S b9 b8 b7 b6 b5 b4 b3 b2 b1 Version b0
b[2:0] ..........Version These bits contain the revision number of the Power Management Interface Specification. hardwired to 001b. b10..............D2S: D2 Support This bit indicates that DS-1E support "D2" of the power state. It is hardwired to "1". They are
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YMF754
54-55h: Power Management Control / Status
Read / Write Default: 0000h Access Bus Width: 8, 16, 32-bit
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 PS b0
b[1:0] ..........PS: Power State These bits determine the power state of DS-1E. "0": "1": "2": "3": D0 D1 D2 D3hot (not supported) DS-1E supports the following power states:
When the power state is changed from D3hot to D0, DS-1E resets the PCI Configuration register 00-3Fh. DS-1E transits to D0 Uninitialized state. Though the power state of this register is changed, the power consumption of DS-1E is not changed. Control / DS-1E Secondary AC'97 Power Control registers. DS-1E can support the power state of D0, D1, D2 and D3 with ACPI. In this case, set ACPI bit (58-59h: ACPI Mode Register) to "1" to disable Capabilities of PCI Bus Power Management. To support low power, Windows driver controls DS-1E Power Control 1 / DS-1E Power Control 2 / DS-1E
58-59h: ACPI Mode
Read / Write Default: 0000h Access Bus Width: 8, 16, 32-bit
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ACPI
b0................ACPI: ACPI Mode Select This bit select either PCI Bus Power Management or ACPI Mode for power management of DS-1E. "0": PCI Bus Power Management is used. (34h) are enabled. "1": ACPI Mode is used. (default) CAP bit and Capabilities Pointer are hardwired "0", and disabled. CAP bit (06-07h: Status Register) and Capabilities Pointer
5A-5Bh: DS-1E Secondary AC'97 Power Control
Read / Write Default: 0000h Access Bus Width: 8, 16, 32-bit
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 SPR7 SPR6 SPR5 SPR4 SPR3 SPR2 SPR1 SPR0
b0................SPR0: Secondary AC'97 Power Down Control 0 This bit controls the power state of the ADC and Input Mux in the Secondary AC'97. "0": Normal "1": Power down (default)
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YMF754
b1................SPR1: Secondary AC'97 Power Down Control 1 This bit controls the power state of the DAC in the Secondary AC'97. "0": Normal "1": Power down b2................SPR2: Secondary AC'97 Power Down Control 2 This bit controls the power state of the Analog Mixer (Vref still on) in the Secondary AC'97. power state retains the Reference Voltage of the AC'97. "0": Normal "1": Power down b3................SPR3: Secondary AC'97 Power Down Control 3 This bit controls the power state of the Analog Mixer (Vref off) in the Secondary AC'97. state removes Reference Voltage of the AC'97. "0": Normal "1": Power down b4................SPR4: Secondary AC'97 Power Down Control 4 This bit controls the power state of the AC-link in the Secondary AC'97. "0": Normal "1": Power down b5................SPR5: Secondary AC'97 Power Down Control 5 Setting this bit to "1" disables the internal clock of the Secondary AC'97. DS-1E, the master clock is supplied from DS-1E. "0": Normal "1": Disable b6................SPR6: Secondary AC'97 Power Down Control 6 This bit controls PR6 bit status of the power control register in the Secondary AC'97. b7................SPR7: Secondary AC'97 Power Down Control 7 This bit controls PR7 bit status of the power control register in the Secondary AC'97. Respective data set to b[7:0] are correspondingly set into the "Power down Ctrl/Stat" register in the Secondary AC'97 via the AC-Link. These are not set into the "Power down Ctrl/Stat" register in the Primary AC'97. (default) In case the AC'97 is used with (default) (default) This power (default) This (default)
Therefore, when the clock is stopped completely, set
SPR5 bits to "1" firstly, then the CMCD bit should be set to "1" after duration of 1ms or longer.
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60-61h: FM Synthesizer Base Address
Read / Write Default: 0388h Access Bus Width: 8, 16, 32-bit
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 FM Synthesizer Base Address
b[15:2] ........FM Synthesizer Base Address This register sets the base address of the FM synthesizer. If b5:I/O bit of 40h register is set to "1", b[9:2] bits are decoded by ignoring b[15:10] bits.
62-63h: Sound Blaster Base Address
Read / Write Default: 0220h Access Bus Width: 8, 16, 32-bit
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Sound Blaster Base Address
b[15:4] ........Sound Blaster Base Address This register sets the base address of the Sound Blaster. If b5:I/O bit of 40h register is set to "1", b[9:4] bits are decoded by ignoring b[15:10] bits.
64-65h: MPU401 Base Address
Read / Write Default: 0330h Access Bus Width: 8, 16, 32-bit
b15 b14 B13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 MPU401 Base Address
b[15:1] ........MPU401 Base Address This register sets the base address of the MPU401. If b5:I/O bit of 40h register is set to "1", b[9:1] bits are decoded by ignoring b[15:10] bits.
66-67h: Joystick Base Address
Read / Write Default: 0201h Access Bus Width: 8, 16, 32-bit
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Joystick Base Address
b[15:0] ........Joystick Base Address This register sets the base address of the Joystick. If b5:I/O bit of 40h register is set to "1", b[9:0] bits are decoded by ignoring b[15:10] bits.
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YMF754
2. ISA Compatible Device
DS-1E contains the following functions to maintain the compatibility with the past ISA Sound Devices. These devices are considered Legacy devices and the functions are referred to as Legacy Audio. Legacy Audio is independent from PCI Audio and can be used simultaneously. The configuration is set in the Legacy Audio Control Register in the PCI Configuration Register space. Basically, these registers are configured by the BIOS. Also, logical device IDs are assigned to the devices to support Plug and Play. logical IDs. To control the device with the BIOS, the logical device IDs must be defined in the PnP BIOS extended ROM space. The logical IDs are determined by how it is configured. IDs and configuration are as follows. Yamaha defines the following
Logical Device ID YMH0100 YMH0101 YMH0102 YMH0103 YMH010A
Functions used (Block) FM
(*)
MPU401 O
SB Pro (*) O
Joystick O
O O
O O O
* The blocks pertain to the following. FM: SB Pro: Points to the FM synthesizer mapped to AdLibBase (0x0388). Points to the Voice Playback section only. However, both
These devices are independent from each other, and can be Enabled/Disabled individually. AdLib and Sound Blaster must be disabled to disable the internal FM Synthesizer. only masks the access.
Disabling just AdLib
The driver by Yamaha supports logical device ID, YMH0100, YMH0102, YMH0103 and YMH010A. For YMH0101, use the driver provided by Microsoft.
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YMF754
DS-1E supports PC/PCI and D-DMA protocols to emulate the DMA of SB Pro on the PCI. 1E supports the old type of interrupts used by ISA and the Serialized IRQ protocol. The combination of PC/PCI and Serialized IRQ is recommended for DS-1E. The system block diagram when using Intel chip set is shown below. In addition, DS-
North Brigde
(430TX/440BX)
PCI
Address/Data Control
PCREQ# PCGNT#
DS-1E
IRQ5 IRQ7 IRQ9 IRQ10 IRQ11 SERIRQ#
South Bridge (PIIX4E)
Select either protocols
The PCI-to-ISA bridge needs to support PC/PCI. PCI-to-ISA bridge.
IRQ is directly connected to the IRQ input pins on the
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YMF754
2-1. FM Synthesizer Block
FM Synthesizer Block is register compatible with YMF289B. However, Power Management register
has been deleted because it is now controlled by the PCI Configuration Register. The following shows the FMBase I/O map of FM Synthesizer. FMBase FMBase FMBase+1 FMBase+2 FMBase+3 (R) (W) (R/W) (W) (R/W) Status Register port Address port for Register Array 0 Data port Address port for Register Array 1 Data port
The following shows the FM Synthesizer Block registers.
2-1-1. Status Register FM Synthesizer Status Register (RO):
Address xxh D7 IRQ D6 FT1 D5 FT2 D4 D3 D2 BUSY D1 D0 BUSY
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YMF754
2-1-2. FM Synthesizer Data Register FM Synthesizer Data Register Array 0 (R/W):
Address 00-01h 02h 03h 04h 08h 20-35h 40-55h 60-75h 80-95h
(*1) (*2) (*3) (*4)
D7
D6
D5
D4
D3
D2
D1
D0
LSI TEST TIMER 1 TIMER 2 RST AM KSL AR SL F-NUM (L) DAM (*6) DVB (*6) KON RHY CHR BD CHL BLOCK SD TOM FB WS F-NUM (H) TC HH CNT MT1 NTS VIB MT2 EGT KSR TL DR RR MULT ST2 ST1 -
A0-A8h B0-B8h BDh C0-C8h E0-F5h
(*5)
FM Synthesizer Data Register Array 1 (R/W)
Address 00-01h 04h 05h 20-35h 40-55h 60-75h 80-95h
(*1) (*2) (*3) (*4)
D7
D6
D5
D4
D3
D2
D1
D0
LSI TEST AM KSL AR SL F-NUM (L) (*6) (*6) KON CHR CHL BLOCK FB WS F-NUM (H) CNT VIB EGT KSR TL DR RR CONNECTION SEL (*6) MULT (*6) NEW
A0-A8h B0-B8h C0-C8h E0-F5h
(*5)
*1 : 26h, 27h, 2Eh and 2Fh do not exist. *2 : 46h, 47h, 4Eh and 4Fh do not exist. *3 : 66h, 67h, 6Eh and 6Fh do not exist. *4 : 86h, 87h, 8Eh and 8Fh do not exist. *5 : E6h, E7h, EEh and EFh do not exist. *6 : The bits exist, but do not function.
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YMF754
2-2. Sound Blaster Pro Block
Sound Blaster Pro block emulates the DSP commands of Sound Blaster and Sound Blaster Pro. playback functions are supported (record functions are not supported). The DMA transfer of this block uses PC/PCI or D-DMA protocol. The following shows the SBBase I/O map of SB Pro. SBBase SBBase SBBase+1h SBBase+2h SBBase+3h SBBase+4h SBBase+5h SBBase+6h SBBase+8h SBBase+8h SBBase+9h SBBase+Ah SBBase+Ch SBBase+Ch SBBase+Eh (R) (W) (R/W) (W) (R/W) (R/W) (R/W) (W) (R) (W) (R/W) (R) (R) (W) (R) FM Synthesizer Status port FM Synthesizer Address port for Register Array 0 FM Synthesizer Data register FM Synthesizer Address port for Register Array 1 FM Synthesizer Data port SB Mixer Address port SB Mixer Data port SB DSP Reset port FM Synthesizer Status port FM Synthesizer Address port for Register Array 0 FM Synthesizer Data port DSP Read Data port DSP Write-buffer status port DSP Write Command/Data port DSP Read-buffer status port compatibility for games, it is designed so that every DSP command receives a correct response. Only
However, to maintain
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YMF754
2-2-1. DSP Command The following shows the list of DSP Commands that are supported by the SB Pro engine. SB Pro commands are supported. Both SB and
CMD Support Function
10h 14h 16h 17h 1Ch 1Fh 20h(*1) 24h(*1) 2Ch(*1) 30h 31h 34h 35h 36h(*2) 37h(*2) 38h 40h 48h 74h 75h 76h 77h 7Dh 7Fh 80h 90h 91h 98h(*1) 99h(*1) A0h(*1) A8h(*1) D0h D1h(*3) D3h(*3) D4h D8h DAh E1h o o 8bit direct mode single byte digitized sound output 8bit single-cycle DMA mode digitized sound output 8bit to 2bit ADPCM single-cycle DMA mode digitized sound output 8bit to 2bit ADPCM single-cycle DMA mode digitized sound output with ref. byte 8bit auto-init DMA mode digitized sound output 8bit to 2bit ADPCM auto-init DMA mode digitized sound output with ref. byte 8bit direct mode single byte digitized sound input 8bit single-cycle DMA mode digitized sound input 8bit auto-init DMA mode digitized sound input Polling mode MIDI input Interrupt mode MIDI input UART polling mode MIDI I/O UART interrupt mode MIDI I/O UART polling mode MIDI I/O with time stamping UART interrupt mode MIDI I/O with time stamping MIDI output Set digitized sound transfer Time Constant Set DSP block transfer size 8bit to 4bit ADPCM single-cycle DMA mode digitized sound output 8bit to 4bit ADPCM single-cycle DMA mode digitized sound output with ref. byte 8bit to 3bit ADPCM single-cycle DMA mode digitized sound output 8bit to 3bit ADPCM single-cycle DMA mode digitized sound output with ref. byte 8bit to 4bit ADPCM auto-init DMA mode digitized sound output with ref. byte 8bit to 3bit ADPCM auto-init DMA mode digitized sound output with ref. byte Pause DAC for a duration 8bit high-speed auto-init DMA mode digitized sound output 8bit high-speed single-cycle DMA mode digitized sound output 8bit high-speed auto-init DMA mode digitized sound input 8bit high-speed single-cycle DMA mode digitized sound input Set input mode to mono Set input mode to stereo Pause 8bit DMA mode digitized sound I/O Turn on speaker Turn off speaker Continue 8bit DMA mode digitized sound I/O Get speaker status Exit 8bit auto-init DMA mode digitized sound I/O Get DSP version number
o o o o o o o o o o o o o o o
o o o o o o o o o o o o o o o
Note: (*1) The SB Block responds correctly to the commands for recording and also executes the DMA transfer. 80h is always transferred. (*2) Only output is supported for this command. (*3) This command only changes Speaker Status (D8h). Undocumented commands other than the ones listed above are also supported.
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YMF754
2-2-2. Sound Blaster Pro Mixer The following shows the register map of the Mixer section of Sound Blaster Pro.
Address 00h 04h 0Ah 0Ch 0Eh 22h 26h 28h 2Eh F0h F1h F2h F3h F4h F8h Voice Volume L Ifilter* Ofilter* "1" "1" "1" "1" "1" "1" "1" "1" SCAN SS DATA Suspend / Resume CFA MPUS SBI IRQ Status b7 b6 b5 b4 Reset Voice Volume R MIC Volume* Input Source* St. SW "1" "1" "1" "1" "1" "1" SE SBPDR SB Pro Mixer "1" b3 b2 b1 b0 Remark
Master Volume L MIDI Volume L CD Volume L* Line Volume L* SBPDA -
Master Volume R MIDI Volume R CD Volume R* Line Volume R* SM
Current FM Synthesizer Index -
FFEMP FFFUL -
The registers marked with * exist, but do not function. DS-1E does not have the circuit that corresponds to the SB Mixer. The conversion for each case is described below. (1) SB Mixer (R) DSP The volume of master, MIDI and Voice, are applied to this case. When the SB register is set, a 14-bit coefficient value is determined from the following conversion table and used as the DSP coefficient. together to obtain the coefficient. These volumes cannot be controlled from PCI Audio block. The attenuation value of Master Volume, MIDI, and voice are summed Therefore, the volume settings on the
SB Mixer are converted to the DSP coefficients of DS-1E or to AC'97 register values.
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YMF754
(1) Volume for MIDI
MIDI Vol. (26h) 0 0 1 2 3 4 5 6 7
mute
0000h
1
mute
0000h
2
mute
0000h
3
mute
0000h
4
mute
0000h
5
mute
0000h
6
mute
0000h
7
mute
0000h
mute
0000h
-52dB
0029h
-42dB
0082h
-36dB
0103h
-32dB
019Bh
-30dB
0206h
-28dB
028Ch
-26dB
0335h
mute
0000h
-42dB
0082h
-32dB
019Bh
-26dB
0335h
-22dB
0515h
-20dB
0666h
-18dB
080Eh
-16dB
0A24h
Master Vol. (22h)
mute
0000h
-36dB
0103h
-26dB
0335h
-20dB
0666h
-16dB
0A24h
-14dB
0CC5h
-12dB
1013h
-10dB
143Dh
mute
0000h
-32dB
019Bh
-22dB
0515h
-16dB
0A24h
-12dB
1013h
-10dB
143Dh
-8dB
197Ah
-6dB
2013h
mute
0000h
-30dB
0206h
-20dB
0666h
-14dB
0CC5h
-10dB
143Dh
-8dB
197Ah
-6dB
2013h
-4dB
2861h
mute
0000h
-28dB
028Ch
-18dB
080Eh
-12dB
1013h
-8dB
197Ah
-6dB
2013h
-4dB
2861h
-2dB
32D6h
mute
0000h
-26dB
0335h
-16dB
0A24h
-10dB
143Dh
-6dB
2013h
-4dB
2861h
-2dB
32D6h
0dB
3FFFh
The default is Master = 4, MIDI = 4 (-12dB). (2) Volume for Voice
Voice Vol. (04h) 0 0 1 2 3 4 5 6 7
mute
0000h
1
mute
0000h
2
mute
0000h
3
mute
0000h
4
mute
0000h
5
mute
0000h
6
mute
0000h
7
mute
0000h
mute
0000h
-56dB
0019h
-46dB
0052h
-40dB
00A3h
-36dB
0103h
-34dB
0146h
-32dB
019Bh
-30dB
0206h
mute
0000h
-46dB
0052h
-36dB
0103h
-30dB
0206h
-26dB
0335h
-24dB
0409h
-22dB
0515h
-20dB
0666Eh
Master Vol. (22h)
mute
0000h
-40dB
00A3h
-30dB
0206h
-24dB
0409h
-20dB
0666h
-18dB
080Eh
-16dB
0A24h
-14dB
0CC5h
mute
0000h
-36dB
0103h
-26dB
0335h
-20dB
0666h
-16dB
0A24h
-14dB
0CC5h
-12dB
1013h
-10dB
143Dh
mute
0000h
-34dB
0146h
-24dB
0409h
-18dB
080Eh
-14dB
0CC5h
-12dB
1013h
-10dB
143Dh
-8dB
197Ah
mute
0000h
-32dB
019Bh
-22dB
0515h
-16dB
0A24h
-12dB
1013h
-10dB
143Dh
-8dB
197Ah
-6dB
2013h
mute
0000h
-30dB
0206h
-20dB
0666h
-14dB
0CC5h
-10dB
143Dh
-8dB
187Ah
-6dB
2013h
-4dB
2861h
The default is Master = 4, Voice = 4 (-16dB). (2) SB Mixer (R) AC'97 The volume of CD, Line and MIC are applied to this case. when these values are changed. the software. AC'97 volume are not updated automatically Thus, the SB Mixer values need to be written to the AC'97 register with
June 28, 1999 -38-
YMF754
2-2-3. SB Suspend / Resume The SB block can read the internal state as to support Suspend and Resume functions. is made up of 268 flip flops. from the SCAN DATA register. These registers are mapped to the SB Mixer space (see SB Mixer Register map). following functions. The registers have the The internal state
To read the state, these states are shifted in order and read 8 bits at a time
F0h: Scan In/ Out Control
Read / Write Default: 00h
b7 SBPDA b6 b5 b4 b3 SS b2 SM b1 SE b0 SBPDR
b0................SBPDR: Sound Blaster Power Down Request This bit stops the internal state of the Sound Blaster block. "0": Normal "1": Stop b1................SE: Scan Enable This bit Shifts the internal state by 1 bit. b2................SM: Scan Mode This bit sets whether to read or write the state. "0": Write "1": Read b3................SS: Scan Select This bit gives permission to read or write the internal data to the SCAN DATA register. "0": Normal operation (Do not allow read or write). "1": Allow read and write. b7................SBPDA: Sound Blaster Power Down Acknowledgement This bit indicates that the SB Block is ready to read or write to the internal state after setting SBPDR. This bit is read only. "0": Read/Write not possible "1": Read/ Write possible (default) (default) Setting a "1" followed by a "0" shifts the internal state. (default)
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YMF754
F1h: Scan In/ Out Data
Read / Write Default: 00h
b7 b6 b5 b4 b3 b2 b1 b0 SCAN DATA
b[7:0] ..........SCAN DATA This is the data port for reading and writing the internal state.
F2h: Current FM Synthesizer Index
Read Only Default: 00h
b7 b6 b5 b4 b3 b2 b1 b0 Current FM Synthesizer Index
b[7:0] ..........Current FM Synthesizer Index This register indicates current index of the FM Synthesizer.
F3h: Current FM Synthesizer Array
Read Only Default: 00h
b7 b6 b5 b4 b3 b2 b1 b0 CFA
b0................CFA: Current FM Synthesizer Arary This bit indicates that the FM Synthesizer array is being currently set to Array 0 or 1. "0": Array 0 "1": Array 1 (default)
F4h: FM Synthesizer / MPU401 Status
Read Only Default: 80h
b7 b6 b5 b4 b3 b2 b1 b0 MPUS FFEMP FFFUL
b0................MPUS: MPU401 Status This bit indicates current MPU401 status. "0": Default mode (Intelligent mode) "1": UART mode b6................FFFUL: FM Synthesizer FIFO Full This bit indicates whether or not FIFO followed by the FM Synthesizer is full. "0": not Full "1": Full (default) (default)
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YMF754
b7................FFEMP: FM Synthesizer Empty This bit indicates whether or not FIFO followed by the FM Synthesizer is empty. "0": not Empty "1": Empty (default)
i) Scan Out
ii) Scan In
: not ready for scanning internal state data
SBPDA=0
SBPDA=0
: not ready for scanning internal state data
SBPDR=1
:
inhibit further DMA, internal state shutdown
SBPDR=1
: inhibit further DMA, internal state shutdown
SBPDA=1
: ready for scanning internal state data
SBPDA=1
: ready for scanning internal state data
SM=1 SS=1
: internal state read out : reading internal state
SM=0 SS=1
:
internal state write in
: writing internal state
SE=1 -> 0
: shifting internal state scan data out 1-bit at a time
Scan Data (Write) SE=1 -> 0
:
internal state scan data in
:
8 times
shifting internal state scan data in 1-bit at a time 8 times
N times
N times
Scan Data (Read)
: internal state scan data out
Suspend Preparation
SM=0 SS=0 SBPDR=0 Resume Completion
N = 34 byte (Total Scan Data = 268 bit (33 byte x 8 + 4 bit))
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YMF754
2-2-4. SB IRQ Status
F8h: Interrupt Flag Register
Read Only Default: 00h
b7 b6 b5 b4 b3 b2 b1 b0 SBI
b0................SBI: SB Interrupt Flag This bit indicates that the SB DSP occurs the interrupt. read port to clearing the interrupt and this bit. This bit is read only. Thus, read the SB DSP
Then, the value of the read port is invalid.
2-3. MPU401
MPU401 block is for transmitting and receiving MIDI data. receiving. The following shows the MPUBase I/O map for MPU401. MPUBase MPUBase + 1h MPUBase + 1h
port +0h +1h (W) +1h (R) /DSR /DRR D7
It is compatible with UART mode of
"MPU401". Full duplex operation is possible using the 16-byte FIFO for each direction, transmitting and
(R/W) (R) (W)
D6
MIDI Data port Status Register port Command Register port
D5 D4 Data Command D3 D2 D1 D0
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YMF754
2-4. Joystick
Joystick Block is the port for connecting IBM compatible analog joystick. The following shows the JSBase I/O map for Joystick. JSBase
Port +0h
(R/W)
D7 JBB2 D6 JBB1 D5 JAB2 D4 JAB1 D3 JBCY D2 JBCX D1 JACY D0 JACX
JACX... JACY... JBCX... JBCY... JAB1... JAB2... JBB1... JBB2...
Joystick A, Coordinate X Joystick A, Coordinate Y Joystick B, Coordinate X Joystick B, Coordinate Y Joystick A, Button 1 Joystick A, Button 2 Joystick B, Button 1 Joystick B, Button 2
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YMF754
3. DMA Emulation Protocol
The former synthesizer LSI for the ISA bus such as the Sound Blaster used the DMA controller (8237: ISA DMAC) on the system to transfer the sound data from/to the host. For DS-1E, however, ISA DMAC must be used to transfer the sound data to the Sound Blaster Pro Block of the Legacy Audio Block. Because signals to connect to the ISA DMAC are generally not available on the PCI bus, there are two ways proposed from the industry to emulate the ISA DMAC on the PCI bus. One is PC/PCI and the other is DDMA. DS-1E supports both protocols for transferring SB Pro sound data on the PCI bus.
3-1. PC/PCI
DS-1E provides two signals, PCREQ# and PCGNT# to realize the PC/PCI. shown below. the DMA channel it is going to use. In addition, DS-1E determines whether the next PCI I/O cycle is its own from the channel information that is encoded in PCGNT#.
0ns PCICLK REQ# GNT# start CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 start bit0 bit1 bit2 100ns 200ns 300ns 400ns
The format of the signals is
DS-1E asserts PCREQ# and sets PCREQ# to "HIGH" using the PCICLK corresponding to
PCGNT# is encoded as follows. bit2 0 0 0 0 1 1 1 1 bit1 0 0 1 1 0 0 1 1 GNT# Encoding bit0 GNT# Bits DMA Channel 0 0 DMA Channel 1 1 DMA Channel 2 0 DMA Channel 3 1 Reserved 0 DMA Channel 5 1 DMA Channel 6 0 DMA Channel 7 1 It also only supports Single DMA transfer.
DS-1E supports only 8-bit DMA channels (DMA Channel 0-3).
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YMF754
3-2. D-DMA
DS-1E provides the following registers to support D-DMA. D-DMA Slave Configuration Register (4C-
4Dh) of the PCI Configuration register is used to set the Base address of the Slave Address. Slave Address Base + 0h Base + 0h Base + 1h Base + 1h Base + 2h Base + 2h Base + 3h Base + 3h Base + 4h Base + 4h Base + 5h Base + 5h Base + 6h Base + 6h Base + 7h Base + 8h Base + 8h Base + 9h Base + Ah Base + Bh Base + Ch Base + Dh Base + Eh Base + Fh R/W W R W R W R W R W R W R W R N/A W R W N/A W W W N/A R/W Register Name Base Address 0-7 Current Address 0-7 Base Address 8-15 Current Address 8-15 Base Address 16-23 Current Address 16-23 Base Address 24-31 Current Address 24-31 Base Word Count 0-7 Current Word Count 0-7 Base Word Count 8-15 Current Word Count 8-15 Base Word Count 16-23 Current Word Count 16-23 Reserved Command Status Request Reserved Mode Reserved Master Clear Reserved Multi-Channel Mask
These registers can be accessed by 8-bit or 16-bit bus width. DS-1E supports 8-bit DMA transfer only.
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YMF754
4. Interrupt Routing
DS-1E supports three types of interrupts, interrupt signal on the PCI bus (INTA#), interrupt signal on the ISA bus (IRQ[5,7,9,10,11]), and Serialized IRQ. The IRQs on DS-1E are routed as shown below.
INTA#
INTA
PCI Audio
SIEN=0, IMOD=1 SIEN=0, IMOD=0
Selector
IRQ
IRQ5 IRQ7 IRQ9 IRQ10 IRQ11
SIEN=1, IMOD=0
Sound Blaster Pro
ISA IRQ
SIEN=0, IMOD=1
Select Signal SBIRQ[2:0]
Selector
SIEN=0, IMOD=0 SIEN=1, IMOD=0
IRQ
MPU401
SERIRQ#
SERIRQ
SIEN, IMOD Select Signal MPUIRQ[2:0]
PCI Audio can only use INTA#, but the Sound Blaster Pro and MPU401 blocks of the Legacy Audio Block can use any of the three protocols. The protocol can be switched using 40-43h (Legacy Audio Control Register) of the PCI Configuration Register.
4-1. Serialized IRQ
Serialized IRQ is a method to encode IRQs of 15 channels into one signal. DS-1E provides the SERIRQ# pin to support Serialized IRQ. Only one channel out of the 5 channels, IRQ5, IRQ7, IRQ9, IRQ10, and IRQ11, can be encoded into the IRQ/Data frame of Serialized IRQ. The IRQ channel is selected using 40h-43h (Legacy Audio Control Register) of the PCI Configuration Register.
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YMF754
5. Hardware Volume Control
The hardware volume control determines the AC'97 master volume without using any software control using the external circuit listed below. Two pins, VOLUP# for increasing the volume and VOLDW# for decreasing the volume, are used.
Push SW 1k VOLUP# Push SW 1k VOLDW# 1000p 1000p
DS-1E provides a shadow register for the AC'97 master volume. master volume, it is always reflected in the shadow register.
When the software accesses the AC'97
Bringing the VOLUP# pin LOW level increments the left and right-channel shadow register by +1.5dB respectively. If either one of channel shadow registers have been already set to maximum value (00000b), If both of channel shadow registers have been already set to maximum values, the corresponding channel shadow register remains in the same value, and the other channel shadow register will only be incremented. they remain in the same values. Bringing the VOLDW# pin LOW level decrements the left and right-channel shadow register by -1.5dB respectively. If either one of channel shadow registers have been already set to minimum value (11111b), If both of channel shadow registers have been already set to minimum values, the corresponding channel shadow register remains in the same value, and the other channel shadow register will only be decremented. they remain in the same values. The master volume for the AC'97 is updated automatically via the AC-Link by setting corresponding values to the shadow registers. When both of the VOLUP# and VOLDW# pins are at LOW level at the same time, the MUTE bit of the shadow register is enabled to automatically set the MUTE bit of the AC'97 master volume via the AC-Link. When either one of the VOLUP# or VOLDW# pins is at LOW level, mute condition of the AC'97 is deactivated via the AC-Link. At this point of time, the master volume is set to the value before the mute. At this time, BUSY is set at the AC'97 control register. When the AC-Link is busy (in case the register is controlled by the AC'97 Control Register), shadow register values will be set to the AC'97 on the next frame.
When the master volume is changed or muted depending on the logic level transition status of the VOLUP# and VOLDW# pins, an interrupt is generated at the host. master volume has been changed. When the AC'97 is not connected or it is placed in power down mode, the shadow register values will remain in the same even if the VOLDW# and VOLUP# pins are at LOW level. The interrupt is used to notify the driver that the
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YMF754
6. Digital Audio Interface
DS-1E supports each system of the SPDIF input/output port compliant with the IEC958 specification.
6-1. SPDIF IN
SPDIF input sampling frequency is 32.0kHz, 44.1kHz or 48.0kHz. In DS-1E, sampling rate of the SPDIF signal incoming from the SPDIFIN pin is converted to 48.0kHz in the frequency rate conversion stage in order to process all the signals at 48.0kHz frequency. If input sampling frequency is 48.0kHz, however, this is resampled at 96.0kHz, then decimated into 48.0kHz frequency. DS-1E supports a direct recording function which records by input sampling rate of the SPDIFIN pin without converting to 48kHz. The input signal applied to the SPDIFIN pin can be also provided as outputs to the SPDIFOUT pin. The SPDIF input is used to be selected between Zoomed Video Port on YMF744B (DS-1S). DS-1E, the both functions can be used at the same time. However, on
6-2. SPDIF OUT
SPDIF output is selected from three types of data indicated below: A : Dolby digital (AC-3) encoded data B : Output data (to be provided to the DAC slot on the AC-link) after digital mixing C : Input data applied to the SPDIFIN pin When the above A and B data are supplied as outputs, output sampling frequency is fixed at 48 kHz, and when the above C data is supplied as an output, output sampling frequency is dependent on the frequency available from the SPDIFIN input pin. Control and category codes of the channel status are provided as sampling rate converter, copyright protection available and commercially available recorded software in accordance with the serial copy management system. generation ones. Such a code arrangement allows output data to be digitally copied only to the next When input signal to the SPDIFIN pin is provided as output, no modification is made for
the channel status, etc., and output data is code-dependent available from the SPDIFIN pin.
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YMF754
7. Zoomed Video Port
Zoomed Video Port is defined in the PC Card Standard (PCMCIA) applicable to the notebook PC or other systems. system. This port is used to directly output video and/or audio signals onto the PCMCIA bus for D/A Its major applications include MPEG decoder card and video capture card, etc. conversion process, and connect them directly to the video and/or audio signal processing chips on the PC Because the video and/or audio signals on the Zoomed Video Port have been output in synchronized condition, DS-1E mixes it with the other audio signals, and outputs to AC'97 or SPDIF. Audio signals to be transferred on the Zoomed Video Port include bit clock (SCLK), L/R clock (LRCK) and serial data (DATA), and they are provided as outputs in the format defined below. I S format.
2
This is generally called
SCLK
DATA
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LRCK LEFT Channel RIGHT Channel
In the Zoomed Video Port, synchronization with a master clock supplied from the bus is inherently required. However, DS-1E can asynchronously process audio signal input via the Zoomed Video Port, eliminating the need for master clock. Sampling rate of the audio signals input via the Zoomed Video Port is resampled to 96.0kHz sampling frequency at the stage followed by the SRC block, then converted to 48.0kHz sampling rate in the SRC block stage. Sampling rates to be supported on the Zoomed Video Port include 22.05kHz, 32.0kHz, 44.1kHz and 48.0kHz. Interface connection arrangement between the DS-1E and the Zoomed Video Port is as illustrated below.
DS-1E ZVBCLK ZVLRCK ZVSDI ZV Port SCLK LRCK DATA MCLK
Open
The Zoomed Video Port is used to be selected between SPDIF input on YMF744B (DS-1S). DS-1E, the both functions can be used at the same time.
However, on
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YMF754
8. Multiple AC'97 & Multi-Channel
DS-1E allows connection with up to two AC'97s, and plays back up to 4-channel PCM data. following applications can be realized. Therefore, the
8-1. AC'97 Digital Docking
AC'97 digital docking can be realized by mounting the secondary AC'97 on the docking station side. Typical example of digital docking connection between DS-1E and AC'97s is represented in the diagram below.
CMCLK CBCLK CSYNC CSDO CSDI0 RST# XTL_IN BIT_CLK SYNC SDATA_OUT SDATA_IN RESET#
Primary AC'97
DS-1E
GPIO2 CSDI1 DOCKEN#
Isolation Buffer
PC Side Docking Station Side
DVDD
XTL_IN BIT_CLK SYNC SDATA_OUT RESET# SDATA_IN
Secondary AC'97 (AC'97 Rev2.1)
When digital docking interface is made with the main side (PC side) powered on, but docking station side powered off, it may be not desirable for the secondary AC'97 that each output signal from the AC-Link is applied to the secondary AC'97 that remains in powered off state. In order to avoid such a situation, it is necessary to place an additional isolation buffer on the PC side (or docking station side).
8-2. 4-Channel Speaker System
4-channel speaker system can be realized by the connection of DS-1E with two 2-channel AC'97s as described at "8-1. AC'97 Digital Docking" or using the AC'97 that includes 4-channel D/A converters. Then, 4-channel PCM data can be played back at one time.
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YMF754
ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings
Item Power Supply Voltage (PVDD, VDD) Power Supply Voltage (CVDD, LVDD) Input Voltage Operating Ambient Temperature Storage Temperature Note : PVSS=VSS=LVSS=0[V] Symbol VDD3 VDD2 VIN TOP TSTG Min. -0.3 -0.3 -0.3 0 -50 Max. 4.6 3.6 5.75 70 125 Unit V V V C C
2. Recommended Operating Conditions
Item Power Supply Voltage (PVDD, VDD) Power Supply Voltage (CVDD, LVDD) Operating Ambient Temperature Note : PVSS=VSS=LVSS=0[V] Symbol VDD3 VDD2 TOP Min. 3.00 2.30 0 Typ. 3.30 2.50 25 Max. 3.60 2.70 70 Unit V V C
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YMF754
3. DC Characteristics
Item High Level Input Voltage 1 High Level Input Voltage 1 Low Level Input Voltage 1 High Level Input Voltage 2 Low Level Input Voltage 2 High Level Input Voltage 3 Low Level Input Voltage 3 High Level Input Voltage 4 Low Level Input Voltage 4 Input Leakage Current High Level Output Voltage 1 Low Level Output Voltage 1 High Level Output Voltage 2 Low Level Output Voltage 2 High Level Output Voltage 3 Low Level Output Voltage 3 High Level Output Voltage 4 Low Level Output Voltage 4 High Level Output Voltage 5 Low Level Output Voltage 5 Input Pin Capacitance Clock Pin Capacitance IDSEL Pin Capacitance Output Leakage Current Power Supply Current Symbol VIN VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 VIH4 VIL4 IIL VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 VOH4 VOL4 VOH5 VOL5 CIN CCLK CIDSEL IOL Normal Power Save (*10) *1 *1 *2 *2 *3 *3 *4 *4 0< VIN < VDD5 *5, IOH1 = -0.5mA *5, IOL1 = 1.5mA *6, IOH2 = -100A *6, IOL2 = 300A *7, IOH3 = -2.0mA *7, IOL3 = 6.0mA *8, IOH4 = -0.5mA *8, IOL4 = 1.5mA *9, IOH5 = -1.5mA *9, IOL5 = 4.5mA Condition Min. -0.5 0.5VDD3 0.7VDD3 0.65VDD3 2.0 -10 0.9VDD3 0.8VDD3 0.9VDD3 2.4 2.4 5 5 5 -10 Typ. 75 TBD Max. 5.75 0.3VDD3 0.3VDD3 0.35VDD3 0.8 10 0.1VDD3 0.2VDD3 0.1VDD3 0.4 0.4 15 15 15 10 100 TBD Unit V V V V V V V V V A V V V V V V V V V V pF pF pF A mA mA
Note : Top = 0~70C, PVDD=3.30.3[V], VDD=3.30.3[V], CVDD=2.50.2[V], LVDD=2.50.2[V] *1: Applicable to all PCI Iuput/Output pins and Iunput pins. *2: Applicable to XI24 pin. *3: Applicable to CBCLK, CSDI0 and CSDI1 pins. *4: Applicable to ZVBCLK, ZVLRCK, ZVSDI, GP[7:4], RXD, VOLUP#, VOLDW#, GPIO[2:0], DOCKEN#, ROMDI, SPDIFIN and TEST# pins. *5: Applicable to all PCI Input/Output pins and output pins. *6: Applicable to XO24 pin. *7: Applicable to CRST#, CSYNC, CSDO and CMCLK pins. *8: Applicable to SPDIFOUT, ROMSK, ROMDO, ROMCS, GPIO[2:0] and TXD pins. *9: Applicable to IRQ5, IRQ7, IRQ9, IRQ10 and IRQ11 pins. *10: All DS-1E Power Control bits are set to "1".
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YMF754
4. AC Characteristics
4-1. Master Clock Item XI24 Cycle Time XI24 High Time XI24 Low Time (Fig.1) Symbol tXICYC tXIHIGH tXILOW Min. 13 13 Typ. 40.69 Max. 24 24 Unit ns ns ns
Note : Top = 0-70C, PVDD=3.30.3 V, VDD=3.30.3 V, CVDD=2.50.2 V, LVDD=2.50.2 V
2.3 V
XI24
1.65 V 1.0 V
t XIHIGH
t XILOW
t XICYC
Fig.1: XI24 Master Clock timing 4-2. Reset (Fig.2) Item Reset Active Time after Power Stable Power Stable to Reset Rising Edge Reset Slew Rate Symbol tRST tRSTOFF Min. 1 10 50 Typ. Max. Unit ms ms mV/ns
Note : Top = 0-70C, PVDD=3.30.3 V, VDD=3.30.3 V, CVDD=2.50.2 V, LVDD=2.50.2 V, CL=50 pF
3.0 V
PVDD, VDD
CVDD, LVDD
2.3 V
t RSTOFF t RST RST#
0.8 V
Fig.2: PCI Reset timing
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YMF754
4-3. PCI Interface Item PCICLK Cycle Time PCICLK High Time PCICLK Low Time PCICLK Slew Rate PCICLK to Signal Valid Delay Float to Active Delay Active to Float Delay Input Setup Time to PCICLK Input Hold Time for PCICLK (Fig.3, 4) Symbol tPCYC tPHIGH tPLOW tPVAL tPON tPOFF tPSU tPSU(PTP) tPH (Bused signal) *11 (Point to Point) *12 (Point to Point) (Bused signal) tPVAL(PTP) (Point to Point) Condition Min. 30 11 11 1 2 2 2 7 10 12 0 Typ. Max. 4 11 12 28 Unit ns ns ns V/ns ns ns ns ns ns ns ns ns
Note : Top = 0-70C, PVDD=3.30.3 V, VDD=3.30.3 V, CVDD=2.50.2 V, LVDD=2.50.2 V, CL=10 pF *11: This characteristic is applicable to REQ# and PCREQ# signal. *12: This characteristic is applicable to GNT# and PCGNT# signal.
0.5 VDD3
PCICLK
0.4 VDD3 0.3 VDD3
t PHIGH t PCYC
t PLOW
Fig.3: PCI Clock timing
1.5 V
PCICLK t PVAL OUTPUT t PON Tri-State OUTPUT t POFF INPUT t PSU
1.5 V
t PH
1.5 V
Fig.4: PCI Bus Signals timing
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YMF754
4-4. AC'97 Master Clock Item CMCLK Cycle Time CMCLK High Time CMCLK Low Time CMCLK Rising Time CMCLK Falling Time (Fig.5) Symbol tCMCYC tCMHIGH tCMLOW tCMR tCMF Min. 8 8 4.6 2.1 Typ. 40.69 Max. Unit ns ns ns ns ns
Note : Top = 0-70C, PVDD=3.30.3 V, VDD=3.30.3 V, CVDD=2.50.2 V, LVDD=2.50.2 V, CL=50 pF
t CMR CMCLK
t CMF
0.8 VDD3 0.5 VDD3 0.2 VDD3
t CMHIGH
t CMLOW
t CMCYC
Fig.5: Master Clock timing for AC'97
June 28, 1999 -55-
YMF754
4-5. AC-link (Fig.6) Item CBCLK Cycle Time CBCLK High Time CBCLK Low Time CSYNC Cycle Time CSYNC High Time CSYNC Low Time CBCLK to Signal Valid Delay Output Hold Time for CBCLK Input Setup Time to CBCLK Input Hold Time for CBCLK Warm Reset Width
*13: This characteristic is applicable to CSYNC and CSDO signal. *14: This characteristic is applicable to CSDI signal.
Symbol tCBICYC tCBIHIGH tCBILOW tCSYCYC tCSYHIGH tCSYLOW tCVAL tCOH tCISU tCIH *13 *13 *14 *14
Condition
Min. 35 35 0 15 5 -
Typ. 81.4 40.7 40.7 20.8 1.3 19.5 1.3
Max. 45 45 20 -
Unit ns ns ns s s s ns ns ns ns s
Note) Top = 0-70C, PVDD=3.30.3 V, VDD=3.30.3 V, CVDD=2.50.2 V, LVDD=2.50.2 V, CL=50 pF
t CBICYC
2.0 V
CBCLK t CBIHIGH t CBILOW t CVAL
1.5 V 0.8 V
t COH
2.0 V
t CSYLOW
SYNC t CSYHIGH t CSYCYC t CVAL CSDO
0.8 V
1.5 V 0.8 V
t COH
2.0 V
t CISU CSDI
t CIH
2.0 V 0.8 V
Fig.6: AC-link timing
June 28, 1999 -56-
YMF754
4-6. Zoomed Video Port Item ZVLRCK Delay Time ZVLRCK Setup Time ZVBCLK Low Time ZVBCLK High Time ZVSDI Setup Time ZVSDI Hold Time (Fig.7) Symbol tSLRD tSLRS tSCLKL tSCLKH tSDS tSDH Min. 2 32 22 22 32 2 Typ. Max. Unit ns ns ns ns ns ns
Note : Top = 0-70C, PVDD=3.30.3 V, VDD=3.30.3 V, CVDD=2.50.2 V, LVDD=2.50.2 V, CL=50 pF
ZVLRCK
tSLRD tSLRS
ZVSCLK
tSDS tSDH tSCLKH t SCLKL
ZVSDI
Fig.7: Zoomed Video Port timing
June 28, 1999 -57-
YMF754
EXTERNAL DIMENSIONS
YMF754-V
22.000.40 20.000.30 0.15Typ. or 0.17Typ.
(LEAD THICKNESS)
102 103
65 64
14.000.30
128 1 38 39 P-0.50Typ. 0.200.10
0 Min. (STAND OFF)
1.400.20
1.70MAX.
(1.00) 0-15 0.500.30
Unit : mm
The shape of the molded corner may slightly different from the shape in this diagram. The figure in the parenthesis ( UNIT : mm Note : The LSIs for surface mount need especial consideration on storage and soldering conditions. For detailed information, please contact your nearest agent of Yamaha. ) should be used as a reference. Plastic body dimensions do not include burr of resin.
16.000.40
June 28, 1999 -58-
YMF754
YMF754-R
16.000.40 14.000.30 96 97 65 64
14.000.30
128 1 0.160.10
0 Min. (STAND OFF)
33 32 P-0.40Typ.
1.70MAX.
1.400.20
(1.0) 0-10
0.500.20 LEAD THICKNESS : 0.125Typ. or 0.15Typ.
Unit : mm
The shape of the molded corner may slightly different from the shape in this diagram. The figure in the parenthesis ( UNIT : mm Note : The LSIs for surface mount need especial consideration on storage and soldering conditions. For detailed information, please contact your nearest agent of Yamaha. ) should be used as a reference. Plastic body dimensions do not include burr of resin.
16.000.40
June 28, 1999 -59-
YMF754
IMPORTANT NOTICE
1. Yamaha reserves the right to make changes to its Products and to this document without notice. The information contained in this document has been carefully checked and is believed to be reliable. However, Yamaha assumes no responsibilities for inaccuracies and makes no commitment to update or to keep current the information contained in this document. 2. These Yamaha Products are designed only for commercial and normal industrial applications, and are not suitable for other uses, such as medical life support equipment, nuclear facilities, critical care equipment or any other application the failure of which could lead to death, personal injury or environmental or property damage. Use of the Products in any such application is at the customer's sole risk and expense. 3. YAMAHA ASSUMES NO LIABILITY FOR INCIDENTAL, CONSEQUENTIAL OR SPECIAL DAMAGES OR INJURY THAT MAY RESULT FROM MISAPPLICATION OR IMPROPER USE OR OPERATION OF THE PRODUCTS. 4. YAMAHA MAKES NO WARRANTY OR REPRESENTATION THAT THE PRODUCTS ARE SUBJECT TO INTELLECTUAL PROPERTY LICENSE FROM YAMAHA OR ANYTHIRD PARTY, AND YAMAHA MAKES NO WARRANTY OR REPRESENTATION OF NON-INFRINGEMENT WITH RESPECT TO THE PRODUCTS. YAMAHA SPECIFICALLY EXCLUDES ANY LIABILITY TO THE CUSTOMER OR ANY THIRD PARTY ARISING FROM OR RELATED TO THE PRODUCTS' INFRINGEMENT OF ANY THIRD PARTY'S INTELLECTUAL PROPERTY RIGHTS, INCLUDING THE PATENT, COPYRIGHT, TRADEMARK OR TRADE SECRET RIGHTS OF ANY THIRD PARTY. 5. EXAMPLES OF USE DESCRIBED HEREIN ARE MERELY TO INDICATE THE CHARACTERISTICS AND PERFORMANCE OF YAMAHA PRODUCTS. YAMAHA ASSUMES NO RESPONSIBILITY FOR ANY INTELLECTUAL PROPERTY CLAIMS OR OTHER PROBLEMS THAT MAY RESULT FROM APPLICATIONS BASED ON THE EXAMPLES DESCRIBED HEREIN. YAMAHA MAKES NO WARRANTY WITH RESPECT TO THE PRODUCTS, EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR USE AND TITLE.
Note) The specifications of this product are subject to improvement change without prior notice.
AGENCY
YAMAHA CORPORATION
Address inquires to : Semi-conductor Sales Department
- Head Office 203, MatsunokiJima, Toyooka-mura. Iwata-gun, Shizuoka-ken, 438-0192 Tel. +81-539-62-4918 Fax. +81-539-62-5054 2-17-11, Takanawa, Minato-ku, Tokyo, 108-8568 Tel. +81-3-5488-5431 Fax. +81-3-5488-5088 1-13-17, Namba Naka, Naniwa-ku, Osaka City, Osaka, 556-0011 Tel. +81-6-6633-3690 Fax. +81-6-6633-3691 YAMAHA System Technology. 100 Century Center Court, San Jose, CA 95112 Tel. +1-408-467-2300 Fax. +1-408-437-8791
- Tokyo Office - Osaka Office
- U.S.A. Office
June 28, 1999 -60-

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